NDLI: Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays

Content Provider	IEEE Xplore Digital Library
Author	Cicek, I. Bozkurt, A. Karaman, M.
Copyright Year	1986
Abstract	Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 /spl times/ 4 array of the designed circuit cells, each cell occupying a 200 /spl times/ 200 /spl mu/m/sup 2/ area, was formed for the initial test studies and scheduled for fabrication in 0.8 /spl mu/m, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.
Page Count	7
File Size	874979
Starting Page	2235
Ending Page	2241
File Format	PDF
ISSN	08853010
Volume Number	52
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Acoustic imaging Acoustic arrays Ultrasonic transducer arrays Pulse amplifiers Performance analysis Circuit testing CMOS technology Ultrasonic transducers Ultrasonic imaging Pulse circuits
Content Type	Text
Resource Type	Article
Subject	Acoustics and Ultrasonics Instrumentation Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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