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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chie, C. |
| Copyright Year | 1972 |
| Abstract | A second-order digital phase-locked loop (DPLL) has a finite lock range which is a function of the frequency of the incoming signal to be tracked. For this reason, it is not capable of tracking an input with Doppler rate for an indefinite period of time. In this correspondence, an analytical expression for the hold-in time is derived. In addition, an all-digital scheme to alleviate this problem is proposed based on the information obtained from estimating the input signal frequency. |
| Starting Page | 1431 |
| Ending Page | 1436 |
| Page Count | 6 |
| File Size | 415918 |
| File Format | |
| ISSN | 00906778 |
| Volume Number | 28 |
| Issue Number | 8 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1980-08-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Frequency locked loops Phase locked loops Tracking loops Frequency estimation Clocks Integrated circuit reliability Costs Digital integrated circuits Large scale integration Very large scale integration |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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