NDLI: Cost-performance evaluation of memory hierarchies

Content Provider	IEEE Xplore Digital Library
Author	Yeong Lin Mattson, R.
Copyright Year	1965
Abstract	The stack processing method is used to compare the cost-performance ($/access) between the following: 1) two-level and three-level hierarchies; and 2) hierarchies using random access and serial access memories as a backing store. It was found that busswidth between levels in the hierarchy strongly affects the system cost-performance, and the access time ratio between the backing store and buffer somewhat less. With the technology cost assumptions used in this study, the three-level hierarchy does not have as good a figure of merit ($/access) as the two-level hierarchy unless the access time ratio exceeds about fifty. Also, random access devices are advantageous over serial access devices for backing store applications only when the memory capacity is less than 1 Mbyte. For capacities of 4 Mbyte and 16 Mbyte serial access stores with shift register lengths of 256 bit and 1024 bit, respectively, look favorable.
Sponsorship	IEEE Magnetics Society
Starting Page	390
Ending Page	392
Page Count	3
File Size	297216
File Format	PDF
ISSN	00189464
Volume Number	8
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1972-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Buffer storage Shift registers Frequency Statistics Laboratories Hardware
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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