NDLI: Time-Offset Injection Method for Neutral-Point AC Ripple Voltage Reduction in a Three-Level Inverter

Content Provider	IEEE Xplore Digital Library
Author	June-Seok Lee Kyo-Beum Lee
Copyright Year	1986
Abstract	The purpose of neutral-point voltage balancing algorithms in the three-level neutral-point clamped (3L-NPC) topology is to eliminate the voltage unbalance of top- and bottom-side dc-link voltages (neutral-point voltage). These algorithms are divided into dc unbalance and ac unbalance compensation methods. The dc unbalance causes distortion of output currents; therefore, this problem has to be solved. The ac unbalance implies that there is an ac ripple in the top- and bottom-side dc-link voltages. In applications using 3L-NPC topology, a large dc-link capacitor value is required to mitigate this ac unbalance problem. As a result, the size and the cost of applications become large and expensive. In this paper, a compensation method for mitigating the ac unbalance of the neutral-point voltage is proposed, which causes the dc-link capacitor value to be small, when a carrier-based pulse width modulation method is applied. The proposed method compensates the ac unbalance of the neutral-point voltage by adding an optimal compensation value to the reference duty signals. This compensation value is calculated simply by currents and reference duty signals. The calculation process of the optimal compensation value is discussed, and the effectiveness of the proposed method is verified with simulations and experiments.
Sponsorship	IEEE Power Electronics Society
Starting Page	1931
Ending Page	1941
Page Count	11
File Size	1982558
File Format	PDF
ISSN	08858993
Volume Number	31
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2016-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Topology Capacitors Mathematical model Voltage control Inverters Pulse width modulation Time-frequency analysis carrier-based pulse width modulation (CB-PWM) Neutral-point clamped (NPC) inverter neutral-point voltage control Carrier-based pulse width modulation (CB-PWM) neutral-point clamped (NPC) inverter
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Research on Neutral-point Balancing Control for Three-level NPC Inverter Based on Correlation between Carrier-based PWM and SVPWM

A carrier-based PWM strategy for three-level neutral-point-clamped voltage source inverters

A Carrier-Based PWM Strategy With Zero-Sequence Voltage Injection for a Three-Level Neutral-Point-Clamped Converter

A new discontinuous PWM method of three-level inverter for neutral-point voltage ripple reduction

Simple carrier-based pulse-width modulation scheme for three-phase four-wire neutral-point-clamped inverters with neutral-point balancing

Design of Neutral-Point Voltage Controller of a Three-Level NPC Inverter With Small DC-Link Capacitors

Study on double modulation wave carrier-based PWM for three-level neutral-point-clamped inverters

Space-Vector Pulsewidth Modulation for Three-Level NPC Converter With the Neutral Point Voltage Control

Contour-Based Dead-Time Harmonic Analysis in a Three-Level Neutral-Point-Clamped Inverter

Time-Offset Injection Method for Neutral-Point AC Ripple Voltage Reduction in a Three-Level Inverter

Similar Documents

Research on Neutral-point Balancing Control for Three-level NPC Inverter Based on Correlation between Carrier-based PWM and SVPWM

A carrier-based PWM strategy for three-level neutral-point-clamped voltage source inverters

A Carrier-Based PWM Strategy With Zero-Sequence Voltage Injection for a Three-Level Neutral-Point-Clamped Converter

A new discontinuous PWM method of three-level inverter for neutral-point voltage ripple reduction

Simple carrier-based pulse-width modulation scheme for three-phase four-wire neutral-point-clamped inverters with neutral-point balancing

Design of Neutral-Point Voltage Controller of a Three-Level NPC Inverter With Small DC-Link Capacitors

Study on double modulation wave carrier-based PWM for three-level neutral-point-clamped inverters

Space-Vector Pulsewidth Modulation for Three-Level NPC Converter With the Neutral Point Voltage Control

Contour-Based Dead-Time Harmonic Analysis in a Three-Level Neutral-Point-Clamped Inverter

Time-Offset Injection Method for Neutral-Point AC Ripple Voltage Reduction in a Three-Level Inverter