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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sengupta, S. Pandit, S. |
| Copyright Year | 1963 |
| Abstract | In this paper, we present a systematic procedure for the design of a channel profile of an epitaxial delta doped channel (EδDC) MOS transistor so that the intrinsic gain (Au) is high and the threshold voltage (VT) mismatch is low. Analytical study shows that a tradeoff relation exists between low VT mismatch and high AV with respect to the thickness of the channel region. Therefore, careful selection of the design parameters is essential in order to have an optimum performance. The performance characteristics of the designed device are subsequently verified through Technology Computer Aided Design simulations. In order to demonstrate the benefits of using optimized EδDC transistor, we compare its performance with that of a reference deeply depleted channel MOS transistor. The performance improvement of using optimized EδDC transistor with respect to the chosen objectives is clearly explained. |
| Sponsorship | IEEE Electron Devices Society |
| Starting Page | 551 |
| Ending Page | 557 |
| Page Count | 7 |
| File Size | 1975898 |
| File Format | |
| ISSN | 00189383 |
| Volume Number | 63 |
| Issue Number | 2 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2016-01-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | MOSFET Doping Epitaxial growth Logic gates Threshold voltage Epitaxial layers VT mismatch. Channel profile optimization epitaxial delta doped channel (EδDC) intrinsic gain screening phenomenon $V_{T}$ mismatch epitaxial delta doped channel ( $\text{E}\delta $ DC) |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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