NDLI: ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

Content Provider	IEEE Xplore Digital Library
Author	Ying Teng Taskin, B.
Copyright Year	1993
Abstract	This paper presents a topology-based solution for a low-skew rotary oscillator array (ROA) clock distribution network design. An ROA-brick structure is proposed that limits the traveling wave oscillation to only two uniform ring rotation directions in the ROA-brick: all the rings in clockwise (CW) direction or all the rings in counter CW direction. An ROA built from the ROA-bricks has the following advantages: 1) similar to the ROA-brick, only two uniform ring rotation directions are feasible in the ROA; 2) the same phase tapping points of all the rings in the ROA are identifiable; and 3) these same phase tapping points of the ROA are independent from the two possible rotation directions. It is mathematically proved that the ROA-brick is the only ROA structure, which can limit the ring rotation direction combinations so as to guarantee the generation of same phase clock signals. The proposed brick-based ROA clock generation and distribution networks are designed for ISPD 10 clock benchmarks demonstrating the gigahertz operation with the low-skew clock generation and distributions through HSPICE.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	2519
Ending Page	2530
Page Count	12
File Size	5800992
File Format	PDF
ISSN	10638210
Volume Number	23
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Oscillators Clocks Topology Structural rings Synchronization Power transmission lines Capacitance synthesis. Clock distribution network design resonant clock synthesis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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