NDLI: Dynamic Slew Enhancement Technique for Improving Transient Response in an Adaptively Biased Low-Dropout Regulator

Content Provider	IEEE Xplore Digital Library
Author	Maity, A. Patra, A.
Copyright Year	2004
Abstract	This brief presents a dynamic slew enhancement technique for improving the transient response in an adaptively biased low-dropout regulator. This is done by introducing FAST and SLOW paths in an adaptive bias loop. The FAST path injects a quick momentary current during a low-to-high load transient, whereas the SLOW path keeps the current large during a high-to-low load step. The dynamic current shoots up to quite a high level as it is combined with adaptive biasing. When the proposed technique is implemented in the 0.18-μm CMOS technology, the experimental results show the effective reduction in the undershoot (67%) and the overshoot (66.7%) while maintaining a low quiescent current of 1.1 μA. The settling times during 0-50-mA and 50-0-mA load transients are improved by 74% and 99.9%, respectively.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	626
Ending Page	630
Page Count	5
File Size	976148
File Format	PDF
ISSN	15497747
Volume Number	62
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Regulators Transient analysis Materials Transient response Bandwidth Logic gates Resistance current mirror Low drop-out regulator transconductance amplifier (OTA) gain enhancement low quiescent current operational transconductance amplifier Current mirror low-dropout regulator
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

A Capacitorless LDO Regulator With Fast Feedback Technique and Low-Quiescent Current Error Amplifier

Design and Analysis of an Adaptively Biased Low-Dropout Regulator Using Enhanced Current Mirror Buffer

An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

Fast transient low-dropout regulator with undershoot and settling time reduction technique

High-Gain Class-AB OTA with Low Quiescent Current

Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror

Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators

A Fast-Transient Low-Dropout Regulator With Load-Tracking Impedance Adjustment and Loop-Gain Boosting Technique

Dynamic Slew Enhancement Technique for Improving Transient Response in an Adaptively Biased Low-Dropout Regulator

Similar Documents

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

A Capacitorless LDO Regulator With Fast Feedback Technique and Low-Quiescent Current Error Amplifier

Design and Analysis of an Adaptively Biased Low-Dropout Regulator Using Enhanced Current Mirror Buffer

An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

Fast transient low-dropout regulator with undershoot and settling time reduction technique

High-Gain Class-AB OTA with Low Quiescent Current

Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror

Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators

A Fast-Transient Low-Dropout Regulator With Load-Tracking Impedance Adjustment and Loop-Gain Boosting Technique

Dynamic Slew Enhancement Technique for Improving Transient Response in an Adaptively Biased Low-Dropout Regulator