NDLI: An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push

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An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage

Content Provider	IEEE Xplore Digital Library
Author	Qu, X. Zhou, Z.-K. Zhang, B. Li, Z.-J.
Copyright Year	2004
Abstract	An output capacitor-free low-dropout regulator (LDO) using a class-AB operational amplifier and an assistant push–pull output stage (APPOS) circuit to enable fast-transient response with ultralow-power dissipation is presented in this brief. The APPOS circuit is proposed to deliver an extra current that is directly proportional to the output current of the class-AB operational amplifier during transient state with an automatic on/off feature. Moreover, the small-signal and large-signal responses of LDO can be separately optimized. As a result, transient performances of LDO are improved significantly without requiring an area-consuming on-chip capacitor anymore. The proposed LDO has been implemented in a standard 0.35-$\mu\hbox{m}$ CMOS process. Experimental results show that the LDO can regulate the output voltage at 1.0 V from a 1.2-V supply voltage for the maximum load current of 100 mA. The output voltage fully recovers within 2.7 $\mu\hbox{s}$ with the load current switching from 100 $\mu\hbox{A}$ to 100 mA at a 1.2- $\mu\hbox{A}$ quiescent current.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	96
Ending Page	100
Page Count	5
File Size	662865
File Format	PDF
ISSN	15497747
Volume Number	60
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Capacitors Regulators Transient analysis System-on-chip Capacitance Steady-state low quiescent current High slew rate low-dropout regulator (LDO)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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