NDLI: Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

Content Provider	IEEE Xplore Digital Library
Author	Laraba, A. Stratigopoulos, H.-G. Mir, S. Naudet, H.
Copyright Year	2004
Abstract	Testing the static performances of high-resolution analog-to-digital converters (ADCs) consumes long test times that are disproportionately high with respect to the test time devoted to other types of circuits embedded in a modern system-on-chip (SoC). In this paper, we review the state-of-the-art of reduced-code linearity test methods for pipeline ADCs and we propose a new approach that increases the efficiency and accuracy of the method. We show that by exploiting some inherent properties in the architecture of pipeline ADCs we can achieve significant static test time reduction while maintaining the accuracy of the standard histogram test. The proposed method is demonstrated on a 55 nm 11-bit 2.5-bits/stage pipeline ADC.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2391
Ending Page	2400
Page Count	10
File Size	2848093
File Format	PDF
ISSN	15498328
Volume Number	62
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Testing Linearity Noise System-on-chip Histograms Standards static testing Analog-to-digital converter testing design-for- test histogram testing linearity testing pipeline analog-to-digital converters reduced-code linearity testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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