NDLI: An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks

Content Provider	IEEE Xplore Digital Library
Author	Hussain, W. Blaquiere, Y. Savaria, Y.
Copyright Year	2004
Description	An open-drain interface circuit and a corresponding interconnect topology is proposed to support bidirectional communication in a field programmable interconnection network (FPIN), similar to those implemented in field programmable gate arrays (FPGAs). The proposed interface can interconnect multiple nodes in a FPIN. With that interface, the interconnection network imitates the behavioral of open-drain (or open-collector) buses (e.g., those following the I²C protocol). Thus, multiple open-drain I/Os from external integrated circuits (ICs) can be connected together through the FPIN by the proposed interface circuit. The interface that has been fabricated in a 0.13 μm CMOS technology takes 65 μm×22 μm per pin. Test results show that several instances of this interface can be interconnected through the proposed interconnect topology. The topology was implemented and tested combining six open-drain I/Os. The interconnect has propagation delays of approximately 0.26·n+51 ns and 0.26·n+94 ns for rising and falling edge transitions respectively, when each pin has a capacitance of 15 pF, where n is the number of interconnected interfaces. These delays and the propagation delays of the FPIN limit the maximum number of interface circuits that can be interconnected for a given communication speed ( I²C fast-mode plus with 3.4 Mbit/s).
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2465
Ending Page	2475
Page Count	11
File Size	3298762
File Format	PDF
ISSN	15498328
Volume Number	62
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Topology Field programmable gate arrays Detectors MOS devices Protocols wafer scale integration (WSI) Active reconfigurable platform bidirectional bus FPGA ${\rm I}^{2}{\rm C}$ bus open collector bus
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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