NDLI: A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator

Content Provider	IEEE Xplore Digital Library
Author	Young-Ju Kim Sang-Hye Chung Kyung-Soo Ha Seung-Jun Bae Lee-Sup Kim
Copyright Year	2004
Abstract	This paper presents a forwarded-clock receiver using a mixing cell integrated injection-locked oscillator (MIILO) and an I/Q generator based on injection-locked oscillator (IQGILO). By using MIILO, jitter tolerance is enhanced by about 1.8 times at high frequency compared to using a conventional injection-locked oscillator. In addition, the proposed receiver is robust against power supply induced jitter (PSIJ) caused by a clock distribution network because jitter tracking bandwidth of IQGILO is always lower than peak frequency of PSIJ regardless of latency mismatch between data and clock. The test chip achieves 9.6 Gb/s data rate with 0.96 mW/Gb/s and occupies only 0.0162 mm² in a 1 V 65 nm CMOS.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2495
Ending Page	2503
Page Count	9
File Size	2649785
File Format	PDF
ISSN	15498328
Volume Number	62
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Jitter Clocks Computer architecture Receivers Correlation Microprocessors Timing quarter-rate clocking Data-jitter mixer forwarded clock receiver injection-locked oscillator jitter correlation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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