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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dae-Hyun Kwon Young-Seok Park Woo-Young Choi |
| Copyright Year | 2004 |
| Abstract | We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be programmed by scanning the dead-zone width of a variable dead-zone BBPD in the time domain. Its linear-like gain characteristics result in less sensitive CDR performance against input jitter and process, voltage, and temperature (PVT) variations. In addition, a built-in on-chip jitter monitor can be easily implemented using our ML-BBPD. A prototype 1.25-Gb/s CDR based on our ML-BBPD with a built-in jitter monitor is realized with 0.18- μm CMOS technology and its performance is successfully verified with measurement. |
| Sponsorship | IEEE Circuits and Systems Society |
| Starting Page | 1472 |
| Ending Page | 1480 |
| Page Count | 9 |
| File Size | 2245024 |
| File Format | |
| ISSN | 15498328 |
| Volume Number | 62 |
| Issue Number | 6 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-01-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Jitter Clocks Monitoring Voltage-controlled oscillators Detectors Temperature measurement Generators on-chip jitter monitoring Clock and data recovery circuit multi-level bang-bang phase detector |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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