NDLI: A Phase-Interpolation and Quadrature-Generation Method Using Parametric Energy Transfer in CMOS

Content Provider	IEEE Xplore Digital Library
Author	Bhardwaj, K. Lee, T.H.
Copyright Year	2004
Abstract	This work focuses on generation of quadrature clocks with high phase accuracy and low noise, while reducing area and power consumption. The design objective is to make these quadrature oscillators suitable for applications in power- and area-constrained SOCs. We demonstrate in this work quadrature clock generation using parametric capacitance modulation in CMOS technology. We present a quadrature-generation method that is based on parametric energy transfer to an LC resonator. The phase-sensitive nature of parametric pumping is used to generate a signal in quadrature with an incoming clock signal. The design also provides the capability of phase interpolation about quadrature, which is useful in many applications. The detailed system implementation is demonstrated and experimentally verified through a prototype in 65 nm CMOS.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1250
Ending Page	1259
Page Count	10
File Size	1466434
File Format	PDF
ISSN	15498328
Volume Number	62
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Capacitance Energy exchange Capacitors Clocks MOS devices Oscillators quadrature generation Clock and data recovery circuits clock generation high-speed transceivers parametric energy transfer parametric system phase interpolation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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