NDLI: A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

Content Provider	IEEE Xplore Digital Library
Author	Kreienkamp, R. Langmann, U. Zimmermann, C. Aoyama, T. Siedhoff, H.
Copyright Year	1966
Abstract	This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	736
Ending Page	743
Page Count	8
File Size	617552
File Format	PDF
ISSN	00189200
Volume Number	40
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS analog integrated circuits Clocks CMOS technology Jitter Interpolation Coupling circuits Voltage-controlled oscillators Energy consumption Threshold voltage Synchronous digital hierarchy half-rate clock and data recovery Analog quadrature phase interpolator chip-to-chip interconnects CMOS
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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