NDLI: Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain

Content Provider	IEEE Xplore Digital Library
Author	Corsonello, P. Frustaci, F. Lanuzza, M. Perri, S.
Copyright Year	2004
Abstract	Scaling down the supply voltage (V_dd) below the transistors threshold voltage (V_th) has become a very popular technique in designing Ultra-Low-Power circuits whose demand has dramatically increased in the last few years. Designing these kinds of circuit is still a challenge, especially when the latest advanced process technologies are employed. The well-known design methodology used in the typical super-threshold domain (V_dd > V_th) cannot be applied to the design of a sub-threshold circuit due to the different transistor current-voltage relationships that hold when V_dd <; V_th. For this reason, designers need supports suitable for the sub-threshold domain. This paper proposes a complete mathematical model able to predict the output behavior of a sub-threshold CMOS inverter. The model proposed here takes into account the effects of the transient variation of the transistor on-current during the gate switching. Moreover, for the first time, over/undershoot effects due to the input-to-output coupling capacitance are taken into account. The proposed model is formed by closed-form expressions able to predict the over/undershoot position, its amplitude and the inverter delay with great accuracy. Furthermore, it can be easily exploited in predicting the delay of cascading inverters, usually used to realize clock buffers. Under Process-Voltage-Temperature variations, the delay of a single inverter realized using a commercial CMOS 45 nm process technology is predicted with a maximum error lower than 16%. Even better results are obtained when the model is applied to inverter chains.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1456
Ending Page	1464
Page Count	9
File Size	2456788
File Format	PDF
ISSN	15498328
Volume Number	61
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Inverters Semiconductor device modeling CMOS integrated circuits Capacitance Predictive models Transistors sub-threshold CMOS Analytical Model over/undershoot propagation delay
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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