NDLI: Parallel Interleaver Design for a High Throughput HSPA<formula formulatype=inline><tex Notation=TeX>$+$</tex></formula>/LTE Multi-Standard Turbo Decoder

Content Provider	IEEE Xplore Digital Library
Author	Guohui Wang Hao Shen Yang Sun Cavallaro, J.R. Vosoughi, A. Yuanbin Guo
Copyright Year	2004
Abstract	To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA +/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm ². When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1376
Ending Page	1389
Page Count	14
File Size	2793753
File Format	PDF
ISSN	15498328
Volume Number	61
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Throughput Computer architecture Clocks Long Term Evolution Hardware VLSI architecture ASIC implementation HSPA$+$ interleaver LTE/LTE-advanced memory contention parallel processing turbo decoder
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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