NDLI: A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems

Content Provider	IEEE Xplore Digital Library
Author	Bucher, M. Kollipara, R.T. Su, B. Gopalakrishnan, L. Prabhu, K. Venkatesan, P.K. Kaviani, K. Daly, B. Stonecypher, B.W.F. Dettloff, W. Stone, T. Heaton, F. Yi Lu Madden, C. Bangalore, S. Eble, J.C. Nguyen, N.M. Lei Luo
Copyright Year	1966
Abstract	This paper describes an asymmetric 6.4-Gb/s memory interface for a wide range of DIMM configurations for desktop and server applications. The link uses a fly-by quadrature forwarded clock to enable fast startup and power-mode transitions on the DRAM and per-bit timing adjustment on the controller to enable the high-speed signaling. Single-ended low-swing near-ground signaling (NGS) is introduced in order to minimize signaling power. Transmitter and receiver equalization are used on the controller, but not the DRAM, in order to save DRAM complexity and power. Architectural and circuit techniques are presented to address the complex signaling and timing environment encountered in the explored configurations. The implemented link achieves 6.4-Gb/s communication over a 3.5-in FR4 PCB trace with a dual-rank dual-in line memory module with better than 9.1-pJ/bit power efficiency for the entire chip.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	127
Ending Page	139
Page Count	13
File Size	4203467
File Format	PDF
ISSN	00189200
Volume Number	49
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Transmitters Random access memory Voltage control Timing Regulators Receivers switching regulator AC-coupled equalizer CMOS integrated circuits DDR4 DDR5 decision-feedback equalizer dual-inline memory module (DIMM) DRAM chips DRAM PHY driver circuit memory controller PHY near-ground signaling quadrature clock forwarding server memory single-ended signaling source-synchronous link
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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