NDLI: Evaluating Neutron Induced SEE in SRAM-Based FPGA Protected by Hardware- and Software-Based Fault Tolerant Techniques

Content Provider	IEEE Xplore Digital Library
Author	Azambuja, J.R. Nazar, G. Rech, P. Carro, L. Lima Kastensmidt, F. Fairbanks, T. Quinn, H.
Copyright Year	1963
Abstract	This paper presents an approach to detect SEEs in SRAM-based FPGAs by using software-based techniques combined with a nonintrusive hardware module. We implemented a MIPS-based soft-core processor in a Virtex5 FPGA and hardened it with software- and hardware-based fault tolerance techniques. First fault injection in the configuration memory bitstream was performed in order to verify the feasibility of the proposed approach, detection rates and diagnosis. Furthermore a neutron radiation experiment was performed at LANSCE. Results demonstrate the possibility of employing more flexible fault tolerant techniques to SRAM-based FPGAs with a high detection rate. Comparisons between bitstream fault injection and radiation test is also presented.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	4243
Ending Page	4250
Page Count	8
File Size	1077760
File Format	PDF
ISSN	00189499
Volume Number	60
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Field programmable gate arrays Microprocessors Fault tolerance Hardware Single event upsets Single event transients single event effects (SEEs) hybrid fault tolerance techniques microprocessors
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

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Error-Rate Estimation Combining SEE Static Cross-Section Predictions and Fault-Injections Performed on HDL-Based Designs

Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA

An Automated SEU Fault-Injection Method and Tool for HDL-Based Designs

Improving Reliability of SRAM-Based FPGAs by Inserting Redundant Routing

An Analysis Based on Fault Injection of Hardening Techniques for SRAM-Based FPGAs

A Low-Overhead Multiple-SEU Mitigation Approach for SRAM-based FPGAs with Increased Reliability

Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs

Compact and Fast Fault Injection System for Robustness Measurements on SRAM-Based FPGAs

Monte Carlo Analysis of the Effects of Soft Errors Accumulation in SRAM-Based FPGAs

Evaluating Neutron Induced SEE in SRAM-Based FPGA Protected by Hardware- and Software-Based Fault Tolerant Techniques

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