NDLI: Reliability Models for SEC/DED Memory With Scrubbing in FPGA-Based Designs

Content Provider	IEEE Xplore Digital Library
Author	Yubo Li Nelson, B. Wirthlin, M.
Copyright Year	1963
Abstract	Block RAMs on field-programmable gate arrays (FPGAs) are susceptible to radiation-induced single-event upsets (SEUs) and are usually protected by fault-tolerant techniques such as single error correction/double error correction (SEC/DED) codes and/or scrubbing. Scrubbing can be divided into two categories based on the mechanism that controls the scrubbing interval. With deterministic scrubbing, each memory location is scrubbed (repaired) on a regular basis and the interval is fixed. With probabilistic scrubbing, a word is checked and corrected any time it is accessed (read or written). In this case, the scrubbing interval is exponentially distributed. This paper presents two mean-time-to-failure (MTTF) models for SEC/DED memory with scrubbing, which can be applied to general applications, including FPGA designs. The first one considers only probabilistic scrubbing but takes into account nonuniform scrub rates for different memory locations. The second model combines both deterministic scrubbing and probabilistic scrubbing into a single model. The proposed models provide more accurate MTTF estimates compared with prior models. An FPGA-based DSP application is studied as an example to show how the proposed models can be used for estimating memory reliability and to reveal the impact of probabilistic scrub rates and memory access distributions on memory reliability.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	2720
Ending Page	2727
Page Count	8
File Size	1440593
File Format	PDF
ISSN	00189499
Volume Number	60
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Probabilistic logic Mathematical model Field programmable gate arrays Equations Error analysis Reliability engineering single-event upset Error correction FPGAs memory fault tolerance reliability modeling
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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