NDLI: Performance Comparisons of III–V and Strained-Si in Planar FETs and Nonplanar FinFETs at Ultrashort Gate Length (12 nm)

Content Provider	IEEE Xplore Digital Library
Author	Seung Hyun Park Yang Liu Kharche, N. Jelodar, M.S. Klimeck, G. Lundstrom, M.S. Luisier, M.
Copyright Year	1963
Abstract	The exponential miniaturization of Si complementary metal-oxide-semiconductor technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Both industry and academia have been studying new device architectures and materials to address this challenge. In preparation for the 12-nm technology node, this paper assesses the performance of the In_0.75Ga_0.25As of III-V semiconductor compounds and strained-Si channel nanoscale transistors with identical dimensions. The impact of the channel material property and the device architecture on the ultimate performance of ballistic transistors is theoretically analyzed. Two-dimensional and three-dimensional real-space ballistic quantum transport models are employed with band structure nonparabolicity. The simulation results indicate three conclusions: 1) the In_0.75Ga_0.25As FETs do not outperform strained-Si FETs; 2) triple-gate Fin-shaped Field Effect Transistor (FinFET) surely represent the best architecture for sub-15-nm gate contacts, independently from the material choice; and 3) the simulations results further show that the overall device performance is very strongly influenced by the source and drain resistances.
Sponsorship	IEEE Electron Devices Society
Starting Page	2107
Ending Page	2114
Page Count	8
File Size	638839
File Format	PDF
ISSN	00189383
Volume Number	59
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Effective mass Logic gates Silicon Performance evaluation triple gate Double gate finFETs III–V versus Si InGaAs metal–oxide–semiconductor FETs real-space effective mass simulations single gate strained-Si
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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