NDLI: TaN and <formula formulatype=inline><tex Notation=TeX>$hbox{Al}_{2}hbox{O}_{3}$</tex></formula> Sidewall Gate-Etch Damage Influence on Program, Erase, and Retention of Sub-50-nm TANOS nand Flash Memory Cells

Content Provider	IEEE Xplore Digital Library
Author	Beug, M.F. Melde, T. Paul, J. Knoefler, R.
Copyright Year	1963
Abstract	The sidewall gate-etch damage influence on the electrical behavior of 48-nm TaN/AI₂O₃/SiN/SiO₂/Si (TANOS) NAND charge-trapping memory cells is investigated in detail. This etch damage occurs at the sidewall of the high work-function TaN metal gate and high-k AI₂O₃ blocking-oxide layers and adversely affects the electrical performance and the mechanical stability of small-ground-rule TANOS cells. Both issues could be solved for 48-nm TANOS cells by the introduction of a new integration scheme, which includes a removable encapsulation liner. This SiN liner protects the TaN sidewall from the etch damage during the aggressive AI₂O₃ high-k etch process. The optimum of the 48-nm electrical cell performance was found for a 4-nm encapsulation liner thickness. In contrast to 48-nm TANOS cells, the encapsulation liner thickness does not affect the electrical performance of large 5-μm-long-and-wide memory cells. The memory cell performance dependence on the TANOS liner thickness and memory cell size is explained by a damaged AI₂O₃ region approximately 3-4 nm thick at the block oxide side wall. As a result, the reported etch damage exhibits a new scaling issue for TANOS memory cells around the 20-nm technology node when the total encapsulation liner thickness approaches half of the memory cell length.
Sponsorship	IEEE Electron Devices Society
Starting Page	1728
Ending Page	1734
Page Count	7
File Size	808790
File Format	PDF
ISSN	00189383
Volume Number	58
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon compounds Aluminum oxide Logic gates Encapsulation Programming Bleaching High K dielectric materials trap-assisted leakage Charge-trap memory devices nand Flash nonvolatile memory oxide traps removable encapsulation liner $\hbox{TaN}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{SiN}/ \hbox{SiO}_{2}/\hbox{Si}$ (TANOS)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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