NDLI: Hybrid parallel motion estimation architecture based on fast top-winners search algorithm

Content Provider	IEEE Xplore Digital Library
Author	Yeong-Kang Lai Lien-Fei Chen Shien-Yu Huang
Copyright Year	1975
Abstract	In this paper, a hybrid parallel motion estimation architecture based on the fast top-winners algorithm is proposed. In the first instance, the fast top-winners search algorithm is discussed based on the pel-subsampling technique to reduce the computational amount of the sum of absolute difference (SAD). Moreover, the four-parallel spiral scanning (4PSP) with the partial distortion elimination (PDE) mechanism is also utilized to early terminate the unnecessary SAD. Therefore, the proposed fast algorithm can not only avoid trapping into the problem of the local minimum but also save the computational operations with a little performance degradation. According to our proposed algorithm, the 4×4 processing element (PE) array and the dual mode SAD tree are proposed to efficiently perform SAD and Sub-SAD which is accumulated based on the pel-subsampling. For the sake of reducing the system memory bandwidth and decreasing the frequency of the memory access, the local memory configuration and the novel memory interleaving organization are proposed to arrange the current data and reference pixels easily, to access the image pixels efficiently, and to achieve the Level C (Lv. C) data reuse scheme.
Sponsorship	IEEE Consumer Electronics Society
File Size	819160
File Format	PDF
ISSN	00983063
Volume Number	56
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pixel Memory management Algorithm design and analysis Hardware Motion estimation Arrays Motion estimation, partial distortion elimination (PDE), pel-subsampling, VLSI
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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