NDLI: Reconfigurable architecture for entropy decoding and inverse transform in H.264

Content Provider	IEEE Xplore Digital Library
Author	Chia-Cheng Lo Shang-Ta Tsai Ming-Der Shieh
Copyright Year	1975
Abstract	Reconfigurable hardware is an effective design option for dealing with the increasing demands of flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods defined in the H.264 standard, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), using a coarse-grain reconfigurable architecture. An analyzing of the similarities and differences between these two decoding processes shows that CAVLC can be effectively merged into a CABAC decoder. Experimental results show that about 1.5K gates can be saved using the proposed reconfigurable cell (RC) architecture, which corresponds to a 25.4% area savings in the implementation of the CAVLC decoder. Using the idle time in RC arrays, the base cell can be extended to carry out the inverse transform with very limited overhead. The proposed entropy decoder design, which operates at 66 MHz, can decode video sequences at Baseline and Main profiles at Level 3.0 under the real-time constraint.
Sponsorship	IEEE Consumer Electronics Society
File Size	729765
File Format	PDF
ISSN	00983063
Volume Number	56
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Context Logic gates Entropy Syntactics Reconfigurable architectures Transforms CAVLC, CABAC, H.264, Reconfigurable architecture
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

Fast Protection of H.264/AVC by Selective Encryption of CAVLC and CABAC for I and P Frames

A low-cost and high efficiency entropy encoder architecture for H.264/AVC

New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC Decoding

A novel architecture for CABAC decoding (H.264/AVC)

RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding

A flexible architecture for the computation of direct and inverse transforms in H.264/AVC video codecs

A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video

High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder

Reconfigurable architecture for entropy decoding and inverse transform in H.264

Similar Documents

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

Fast Protection of H.264/AVC by Selective Encryption of CAVLC and CABAC for I and P Frames

A low-cost and high efficiency entropy encoder architecture for H.264/AVC

New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC Decoding

A novel architecture for CABAC decoding (H.264/AVC)

RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding

A flexible architecture for the computation of direct and inverse transforms in H.264/AVC video codecs

A flexible fully hardwired CABAC encoder for UHDTV H.264/AVC high profile video

High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coder

Reconfigurable architecture for entropy decoding and inverse transform in H.264