NDLI: A New Algorithm for High-Speed Modular Multiplication Design

Content Provider	IEEE Xplore Digital Library
Author	Ming-Der Shieh Jun-Hong Chen Wen-Ching Lin Hao-Hsuan Wu
Copyright Year	2004
Abstract	Modular exponentiation in public-key cryptosystems is usually achieved by repeated modular multiplications on large integers. Designing high-speed modular multiplication is thus very crucial to speed up the decryption/encryption process. In this paper, we first explore how to relax the data dependency that exists between multiplication, quotient determination, and modular reduction in the conventional Montgomery modular multiplication algorithm. Then, we propose a new modular multiplication algorithm for high-speed hardware design. The speed improvement is achieved by reducing the critical path delay from the 4-to-2 to 3-to-2 carry-save addition. The resulting time complexity of our development is further decreased by simultaneously performing the multiplication and modular reduction processes. Experimental results show that the developed modular multiplication can operate at speeds higher than those of related work. When the proposed modular multiplication is applied to modular exponentiation, both time and area-time advantages are obtained.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2009
Ending Page	2019
Page Count	11
File Size	550296
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Public key cryptography Hardware Very large scale integration Security Circuits Councils Propagation delay Throughput very large scale integration (VLSI) architecture Carry-save addition (CSA) modular exponentiation Montgomery modular multiplication Rivest–Shamir–Adleman (RSA) cryptosystem
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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