NDLI: Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

Content Provider	IEEE Xplore Digital Library
Author	Jun He Sanyi Zhan Degang Chen Geiger, R.L.
Copyright Year	2004
Abstract	When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the model: 1) static offset voltages from the mismatch in muC_ox and threshold voltage V_th and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	911
Ending Page	919
Page Count	9
File Size	1672716
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Threshold voltage Analytical models CMOS technology Semiconductor device modeling Feedback Transient response Parasitic capacitance Topology SPICE Monte Carlo methods static offset voltage Dynamic comparators dynamic offset voltage Monte Carlo method
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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R.J.Geiger,”Analysis of static and dynamic random offset voltages in dynamic comparators,”IEEE Trans. Circuits and Syst.I,reg.papers,vol.56,no.5,pp.911-919,May2009

A simple and accurate method to predict offset voltage in dynamic comparators

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Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

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R.J.Geiger,”Analysis of static and dynamic random offset voltages in dynamic comparators,”IEEE Trans. Circuits and Syst.I,reg.papers,vol.56,no.5,pp.911-919,May2009

A simple and accurate method to predict offset voltage in dynamic comparators

Analytical transient response and propagation delay model for nanoscale CMOS inverter

Predictive expression of propagation delay in short channel CMOS/SOI inverter using Monte Carlo simulation

Transient analysis of CML and CMOS inverters using Monte Carlo simulation

Modeling and analysis of non-rectangular transistors caused by lithographic distortions

Methodology of MOSFET characteristics fluctuation description using BSIM3v3 SPICE model for statistical circuit simulations

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CMOS design challenges to power wall

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators