NDLI: An Embedded 65 nm CMOS Baseband IQ 48 MHz–1 GHz Dual Tuner for DOCSIS 3.0

Content Provider	IEEE Xplore Digital Library
Author	Gatta, F. Gomez, R. Shin, Y.J. Hayashi, T. Hanli Zou Chang, J.Y.C. Dauphinee, L. Jianhong Xiao Chang, D.S.-H. Tai-Hong Chih Brandolini, M. Dongsoo Koh Hung, B.J.-J. Tao Wu Introini, M. Cusmai, G. Zencir, E. Singor, F. Eberhart, H. Tan, L.K. Currivan, B. Lin He Cangiane, P. Vorenkamp, P.
Copyright Year	1966
Abstract	An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	3511
Ending Page	3525
Page Count	15
File Size	2879460
File Format	PDF
ISSN	00189200
Volume Number	44
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Baseband Tuners Cable TV Bandwidth CMOS technology Modems Power harmonic filters Phase locked loops Signal to noise ratio Quadrature amplitude modulation variable-gain low-noise amplifier (VGLNA) ACI ADC Annex A Annex B baseband IQ cable modem CATV tuners CMOS CSO CTB DAC DC offset loops direct digital frequency synthesizer (DDFS) DOCSIS 3.0 downstream power management (DPM) down-stream channels (DS) harmonic rejection RF front-end (HR RFFE) image rejection local oscillator (LO) low IF noise figure (NF) SCTE40 set-top box signal-to-noise ratio (SNR) 64 QAM SOC 256 QAM variable-gain amplifier (VGA)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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