NDLI: A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

Content Provider	IEEE Xplore Digital Library
Author	Van Helleputte, N. Gielen, G.
Copyright Year	1966
Abstract	This paper presents an integrated ultra-low power analog front-end (AFE) architecture for UWB impulse radio receivers. The receiver is targeted towards applications like wireless sensor networks typically requiring ultra energy-efficient, low data-rate communication over a relative short range. The proposed receiver implements pulse correlation in the analog domain to severely relax the power consumption of the ADCs and digital backend. Furthermore a fully integrated prototype of the analog front-end, containing a PLL, programmable clocking generator, analog pulse correlator, a linear-in-dB variable gain amplifier and a 4-bit ADC, is demonstrated. Several design decisions and techniques, like correlation with a windowed LO instead of with a matched template, exploiting the duty-cycled nature of the system, operation in the sub-1 GHz band as well as careful circuit design are employed to reach ultra-low power consumption. The analog front-end was manufactured in 130 nm CMOS and the active circuit area measures 1000 mum times 1500 mum. A maximum channel conversion gain of 50 dB can be achieved. Two symbol rates, 39.0625 M pulses per second (Mpps) and 19.531 Mpps are supported. The AFE consumes 2.3 mA from a 1.2 V power supply when operating at 39.0625 Mpps. This corresponds to an energy consumption of 70 pJ/pulse. A wireless link over more than 10 m in an office-like environment has been demonstrated at 19.531 Mpps with a PER < 1E -3 under direct LOS conditions.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1862
Ending Page	1871
Page Count	10
File Size	1576888
File Format	PDF
ISSN	00189200
Volume Number	44
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Receivers Pulse amplifiers Energy consumption Gain Pulsed power supplies Wireless sensor networks Energy efficiency Prototypes Phase locked loops Clocks VGA ADC analog front-end impulse radio mixer PLL UWB
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 46pJ/pulse analog front-end in 130nm CMOS for UWB impulse radio receivers

A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging

An I/Q based CMOS Pulsed Ultra Wideband Receiver Front End for the 3.1 to 10.6 GHz Band

3.1-4.7GHz WiMedia UWB RF/Analog Front-End in 130nm CMOS

An Ultra-low-Power Quadrature PLL in 130nm CMOS for Impulse Radio Receivers

A 2Gbps RF-correlation-based impulse-radio UWB transceiver front-end in 130nm CMOS

A 5.2 pJ/pulse impulse radio pulse generator in 90 nm CMOS

A symbol-duty-cycled 440 pJ/b impulse radio receiver with 0.57 aJ sensitivity in 130 nm CMOS

Analog front-end RX design for UWB impulse radio in 90nm CMOS

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

Similar Documents

A 46pJ/pulse analog front-end in 130nm CMOS for UWB impulse radio receivers

A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging

An I/Q based CMOS Pulsed Ultra Wideband Receiver Front End for the 3.1 to 10.6 GHz Band

3.1-4.7GHz WiMedia UWB RF/Analog Front-End in 130nm CMOS

An Ultra-low-Power Quadrature PLL in 130nm CMOS for Impulse Radio Receivers

A 2Gbps RF-correlation-based impulse-radio UWB transceiver front-end in 130nm CMOS

A 5.2 pJ/pulse impulse radio pulse generator in 90 nm CMOS

A symbol-duty-cycled 440 pJ/b impulse radio receiver with 0.57 aJ sensitivity in 130 nm CMOS

Analog front-end RX design for UWB impulse radio in 90nm CMOS

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers