NDLI: An I/Q based CMOS Pulsed Ultra Wideband Receiver Front End for the 3.1 to 10.6 GHz Band

Content Provider	IEEE Xplore Digital Library
Author	Vereecken, W. Steyaert, M.S.J.
Copyright Year	2006
Description	Author affiliation: ESAT-MICAS, Katholieke Univ., Leuven (Vereecken, W.; Steyaert, M.S.J.)
Abstract	A pulsed ultra wideband receiver front end for the 3.1 to 10.6 GHz band is implemented in a main-stream 0.18 mum CMOS technology. The monolithic UWB receiver incorporates a mixed-signal multiphase clock generator together with an analog demodulation and amplifier chain on a die of 1.4times1.4 $mm^{2}.$ A dual in-phase/quadrature (I/Q) receiver approach, enabling phase modulation of the UWB impulses, is presented and experimentally demonstrated. The design is optimized to cope with the large bandwidths at the RF input stage and the output buffers are able to directly drive an external analog-to-digital converter (ADC). The receiver consumes 120 mW from a single 1.8 V power supply and is capable to detect 107 M pulses per second. Data transfer up to 428 Mbit/s is possible when a 16-PSK modulation scheme is applied, but can be easily scaled down according to the actual signal-to-noise (SNR) parameters
Starting Page	191
Ending Page	194
File Size	4510098
Page Count	4
File Format	PDF
ISBN	1424401011
DOI	10.1109/ICU.2006.281538
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	UWB Pulsed power supplies Phase modulation Pulse amplifiers CMOS analog integrated circuits Design optimization Broadband amplifiers radio frequency (RF) ultra-wideband CMOS technology Radiofrequency amplifiers radio receiver Ultra wideband technology Clocks Demodulation
Content Type	Text
Resource Type	Article

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