NDLI: Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

Content Provider	IEEE Xplore Digital Library
Author	Smith, A.M. Constantinides, G.A. Cheung, P.
Copyright Year	1993
Abstract	This paper is concerned with the application of formal optimization methods to the design of mixed-granularity field-programmable gate arrays (FPGAs). In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and lookup table (LUT)-based logic, in order to maximize the performance of a set of digital signal processing (DSP) benchmark applications, given a fixed silicon budget. A mathematical programming framework is introduced, along with a set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, we use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context. The approach detailed provides a formal mechanism to explore future technology nodes.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	733
Ending Page	744
Page Count	12
File Size	950037
File Format	PDF
ISSN	10638210
Volume Number	16
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Digital signal processing Optimization methods Design methodology Table lookup Logic devices Reconfigurable logic Logic programming Silicon Mathematical programming reconfigurable architectures Floorplanning field-programmable gate array (FPGA) integer linear programming (ILP) module-selection
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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