NDLI: 3-D Topologies for Networks-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Pavlidis, V.F. Friedman, E.G.
Copyright Year	1993
Abstract	Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40% and 36% and a decrease of 62% and 58% in power consumption is demonstrated for 3D NoC as compared to a traditional 2D NoC topology for a network size of N = 128 and N = 256 nodes, respectively.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	1081
Ending Page	1090
Page Count	10
File Size	877742
File Format	PDF
ISSN	10638210
Volume Number	15
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network topology Network-on-a-chip Energy consumption Integrated circuit interconnections Communication channels Delay Circuit topology Consumer electronics CMOS technology Performance analysis topologies 3-D circuits 3-D integrated circuits (ICs) 3-D integration networks-on-chip (NoC)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

3-D Topologies for Networks-on-Chip

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks

Power characteristics of Networks on Chip

3-D Topologies for Networks-on-Chip (2006)

3-D Topologies for Networks-on-Chip

Similar Documents

3-D Topologies for Networks-on-Chip

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks

Power characteristics of Networks on Chip

3-D Topologies for Networks-on-Chip (2006)

3-D Topologies for Networks-on-Chip