NDLI: Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

Content Provider	IEEE Xplore Digital Library
Author	Kranti, A. Armstrong, G.A.
Copyright Year	1963
Abstract	In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic dc gain (A_VO) and cutoff frequency (f_T) for 60 and 30 nm FinFETs operated at low drive current (J_ds = 5 muA/mum). The improved A_VO and f_T are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio-a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.
Sponsorship	IEEE Electron Devices Society
Starting Page	3308
Ending Page	3316
Page Count	9
File Size	662639
File Format	PDF
ISSN	00189383
Volume Number	54
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage control MOSFET Gain Analog computer circuits ultra-low-voltage (ULV) analog design Capacitances cutoff frequency Early voltage FinFETs intrinsic voltage gain source/drain extension (SDE) region engineering transconductance-to-current ratio
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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