NDLI: Multifrequency TAM design for hierarchical SOCs

Content Provider	IEEE Xplore Digital Library
Author	Qiang Xu Nicolici, N.
Copyright Year	1982
Abstract	The emergence of megacores in hierarchical system-on-a-chip (SOC) presents new challenges to electronic test automation. This paper describes a new framework for designing test access mechanisms (TAMs) for modular testing of hierarchical SOCs. We first explore the concept that TAMs on the same level of design hierarchy employ multiple frequencies for test data transportation. Then we extend this concept to hierarchical SOCs and, by introducing frequency converters at the inputs and outputs of the megacores, the proposed solution not only removes the constraint that the system level TAM width must be wider than the internal TAM width of the megacores, but also facilitates rapid exploration of the tradeoffs between the test application time and the required test area. Experimental results for the ITC'02 SOC Test Benchmarks show that the proposed TAM design algorithms increase the size of the solution space that is explored, which, in turn, will lower the test application time when compared to the existing solutions.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	181
Ending Page	196
Page Count	16
File Size	657407
File Format	PDF
ISSN	02780070
Volume Number	25
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip System testing Space exploration Electronic equipment testing Automatic testing Automation Transportation Frequency conversion Benchmark testing Algorithm design and analysis test access mechanism Electronic test mega-cores system-on-a-chip
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Test planning for modular testing of hierarchical SOCs

Test infrastructure design for mixed-signal SOCs with wrapped analog cores

Time/Area tradeoffs in testing hierarchical SOCs with hard mega-cores (2004)

Testing Chips With Spare Identical Cores

System-on-a-chip test-data compression and decompression architectures based on Golomb codes

Constraint-Driven Test Scheduling for NoC-Based Systems

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Formulating SoC test scheduling as a network transportation problem

Test Planning for Modular Testing of Hierarchical SOCs (2005)

Multifrequency TAM design for hierarchical SOCs

Similar Documents

Test planning for modular testing of hierarchical SOCs

Test infrastructure design for mixed-signal SOCs with wrapped analog cores

Time/Area tradeoffs in testing hierarchical SOCs with hard mega-cores (2004)

Testing Chips With Spare Identical Cores

System-on-a-chip test-data compression and decompression architectures based on Golomb codes

Constraint-Driven Test Scheduling for NoC-Based Systems

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

Formulating SoC test scheduling as a network transportation problem

Test Planning for Modular Testing of Hierarchical SOCs (2005)

Multifrequency TAM design for hierarchical SOCs