NDLI: Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

Content Provider	IEEE Xplore Digital Library
Author	Fiorenza, J.K. Sepke, T. Holloway, P. Sodini, C.G. Hae-Seung Lee
Copyright Year	1966
Abstract	A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	2658
Ending Page	2668
Page Count	11
File Size	1142952
File Format	PDF
ISSN	00189200
Volume Number	41
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Switched capacitor circuits CMOS analog integrated circuits Operational amplifiers Switching circuits Charge transfer Prototypes Pipelines Energy consumption Analog circuits switched-capacitor circuits A/D ADC analog-to-digital conversion CBSC comparator-based switched-capacitor circuits pipeline scaled CMOS
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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