NDLI: A pipelined front-end, timing, and amplitude digitizing system

Content Provider	IEEE Xplore Digital Library
Author	Lan, K.A. Cui, Y. Hungerford, E.V.
Copyright Year	1963
Abstract	A front-end digitizing system is needed for the straw tracking-detector of the MECO experiment. This detector has 24 000 channels of time and amplitude readout. The system operates in a high singles count-rate environment, and continuously digitizes the incoming pulses of every channel, using a latency buffer to temporarily hold this information. For each event, channel occupancy signals are sent to a local logic analyzer. Thus, the system can be self-triggered or triggered by a coincidence of the internally generated occupancy signal with an external gate. Upon presentation of a valid trigger, all data stored in the latency buffer are then read with zero-suppression to local RAM. The readout can provide sub-nanosecond timing and 6-9-bit amplitude resolution. This digitizer design will be implemented in an ASIC due to the large number of readout channels, the requirement that the data initially flow in parallel because of high single rates, and the large number of memory buffers. The digitizer is controlled by an FPGA, and the system clock can be varied between 15-60 MHz. This paper presents the conceptual design for the MECO readout system, but we anticipate that it can be used for many other applications requiring the acquisition of time and waveform signals in high counting rate environments.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	2362
Ending Page	2367
Page Count	6
File Size	557466
File Format	PDF
ISSN	00189499
Volume Number	51
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Delay Buffer storage Detectors Logic Signal analysis Signal generators Read-write memory Signal resolution Application specific integrated circuits
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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