NDLI: Concurrent transient fault simulation for analog circuits

Content Provider	IEEE Xplore Digital Library
Author	Junwei Hou Chatterjee, A.
Copyright Year	1982
Abstract	This paper presents a novel concurrent fault simulation algorithm for nonlinear analog circuits. Between successive time steps in transient fault simulation, all faulty circuits in the fault list are simulated before the simulator proceeds to the next step. Four primary techniques, including fault grouping, fault ordering, state prediction, and reduced-order fault matrix computation, are proposed to significantly reduce analog fault simulation complexity by making use of the similarities between the faulty and fault-free circuits. The method has been implemented in a dc and transient fault simulator called CONCERT2, which is the first ever for nonlinear analog circuits. Up to two orders of magnitude speedup is obtained for complete transient fault simulation, without loss of accuracy in fault detection. It is shown that the methodology of CONCERT2 can significantly speed up the process of analog test stimulus generation.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1385
Ending Page	1398
Page Count	14
File Size	1060499
File Format	PDF
ISSN	02780070
Volume Number	22
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit simulation Analog circuits Computational modeling Circuit testing Electrical fault detection Nonlinear equations System testing Fault diagnosis Circuits and systems
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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