NDLI: Test generation and optimization for DRAM cell defects using electrical simulation

Content Provider	IEEE Xplore Digital Library
Author	Al-Ars, Z. van de Goor, A.J.
Copyright Year	1982
Abstract	Although electrical simulation has become a vital tool in the design process of memory devices, memory testing has not yet been able to employ electrical simulation as an integral part of the test generation and optimization process. This is due to the exponential complexity of the simulation-based fault analysis, a complexity that made such an analysis impractical. This paper describes new methods to reduce the complexity of the fault analysis from exponential to constant with respect to the number of analyzed operations, thereby making it possible: 1) to use electrical simulation to generate test patterns; and 2) to perform simulation-based stress optimization of tests. The paper also discusses ways to analyze the impact of idle time on the faulty behavior. In addition, results of a fault analysis study performed to verify the new analysis method are shown, where the new analysis reduces the analysis time by a factor of 30.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1371
Ending Page	1384
Page Count	14
File Size	773467
File Format	PDF
ISSN	02780070
Volume Number	22
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Random access memory Performance analysis Analytical models Pattern analysis Process design Design optimization Test pattern generators Performance evaluation Stress
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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