NDLI: Validation and test issues related to noise induced by parasitic inductances of VLSI interconnects

Content Provider	IEEE Xplore Digital Library
Author	Sinha, A. Gupta, S.K. Breuer, M.A.
Copyright Year	1999
Abstract	Shows the results of studies of noise induced by various combinations of parasitic capacitances and inductances. Interconnects are simulated with parameters obtained from a 0.18 /spl mu/m process. The four kinds of noise addressed are (i) crosstalk pulse; (ii) crosstalk speedup and slowdown; (iii) oscillatory noise; (iv) combination of oscillatory noise and crosstalk pulse. The crosstalk effects induced by a combination of mutual capacitance and mutual inductance can be larger than those induced by mutual capacitance alone, even if capacitive crosstalk dominates. For certain interconnects that are capacitively and inductively coupled, transitions in the same direction on an aggressor and victim line can cause speedup or slowdown, depending on timing parameters. A similar observation holds for transitions in opposite directions. We also observe that oscillatory noise can combine with crosstalk pulse under certain skew conditions and give rise to a large magnitude of noise. We show that inductance induced noise can be a problem in medium length interconnects. Because such interconnects can occur in combinational logic blocks, the generation of suitable vectors for test and validation of such logic blocks is of concern.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society IEEE Components, Packaging and Manufacturing Technology Society
Starting Page	329
Ending Page	339
Page Count	11
File Size	575444
File Format	PDF
ISSN	15213323
Volume Number	25
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Crosstalk Semiconductor device noise Inductance Delay Capacitance Logic testing Signal to noise ratio Circuit noise Timing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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