NDLI: A hardware cost minimized fast Phong shader

Content Provider	IEEE Xplore Digital Library
Author	Hyun-Chul Shin Jin-Aeon Lee Lee-Sup Kim
Copyright Year	1993
Abstract	One of the most successful algorithms that bring realism to the world of three-dimensional (3-D) image generation is Phong shading. With the continuous improvement in VLSI technology and the demand for higher realism, this algorithm is amenable to the commercially available hardware implementation for real-time rendering in 3-D graphics. Taylor series approximation is appropriate for the hardware implementation of fast Phong shading. However, in this method, the exponentiation of the cosine term requires a very large ROM table. This paper describes the minimization of this overhead in terms of hardware size by proposing an adaptive-compressed nonuniform quantization method. With this method, the ROM table is reduced to 1/64th of the size required for a uniform quantization method while the picture quality is maintained. Due to the reduced ROM table size, the size of the total hardware required for fast Phong shading is minimized to 1/56th of the original size.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	297
Ending Page	304
Page Count	8
File Size	226772
File Format	PDF
ISSN	10638210
Volume Number	9
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Costs Read only memory Quantization Image generation Continuous improvement Very large scale integration Rendering (computer graphics) Graphics Taylor series
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics

VLSI implementation of Phong shader in 3D graphics

A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth

A low-cost graphics and multimedia workstation chip set

A design methodology achieving fast development cycles for complex VLSI architectures

Entertainment and Edutainment

A New VLSI Architecture for Turbo Decoder Employing De-interleaver Table Free Method

A Fast Spline Curve Rendering Accelerator Architecture

Real-time VQ codebook generation hardware for speech processing

A hardware cost minimized fast Phong shader

Similar Documents

A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics

VLSI implementation of Phong shader in 3D graphics

A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth

A low-cost graphics and multimedia workstation chip set

A design methodology achieving fast development cycles for complex VLSI architectures

Entertainment and Edutainment

A New VLSI Architecture for Turbo Decoder Employing De-interleaver Table Free Method

A Fast Spline Curve Rendering Accelerator Architecture

Real-time VQ codebook generation hardware for speech processing

A hardware cost minimized fast Phong shader