NDLI: An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

Content Provider	IEEE Xplore Digital Library
Author	Henkel, J. Ernst, R.
Copyright Year	1993
Abstract	Hardware/software partitioning is a key issue in the design of embedded systems when performance constraints have to be met and chip area and/or power dissipation are critical. For that reason, diverse approaches to automatic hardware/software partitioning have been proposed since the early 1990s. In all approaches so far, the granularity during partitioning is fixed, i.e., either small system parts (e.g., base blocks) or large system parts (e.g., whole functions/processes) can be swapped at once during partitioning in order to find the best hardware/software tradeoff. Since the deployment of a fixed granularity is likely to result in suboptimum solutions, we present the first approach that features a flexible granularity during hardware/software partitioning. Our approach is comprehensive in so far that the estimation techniques, our multigranularity performance estimation technique described here in detail, that control partitioning, are adapted to the flexible partitioning granularity. In addition, our multilevel objective function is described. It allows us to tradeoff various design constraints/goals (performance/hardware area) against each other. As a result, our approach is applicable to a wider range of applications than approaches with a fixed granularity. We also show that our approach is fast and that the obtained hardware/software partitions are much more efficient (in terms of hardware effort, for example) than in cases where a fixed granularity is deployed.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	273
Ending Page	289
Page Count	17
File Size	466967
File Format	PDF
ISSN	10638210
Volume Number	9
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Application software Embedded software Software performance Embedded system Power dissipation System-on-a-chip Software systems Silicon National electric code
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Multi-Granularity Power Modeling Methodology for Embedded Processors

System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip

System-level power-performance tradeoffs for reconfigurable computing

Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

Power estimation of embedded systems: a hardware/software codesign approach

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems

Timed compiled-code functional simulation of embedded software for performance analysis of SOC design

Low-power instruction bus encoding for embedded processors

Power analysis of embedded software: a first step towards software power minimization

An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

Similar Documents

A Multi-Granularity Power Modeling Methodology for Embedded Processors

System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip

System-level power-performance tradeoffs for reconfigurable computing

Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

Power estimation of embedded systems: a hardware/software codesign approach

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems

Timed compiled-code functional simulation of embedded software for performance analysis of SOC design

Low-power instruction bus encoding for embedded processors

Power analysis of embedded software: a first step towards software power minimization

An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques