NDLI: Precision flip-chip solder bump interconnects for optical packaging

Content Provider	IEEE Xplore Digital Library
Author	Imler, W.R. Scholz, K.D. Cobarruviaz, M. Nagesh, V.K. Chao, C.C. Haitz, R.
Copyright Year	1978
Abstract	Solder bump flip-chip technology is particularly well suited to the packaging of classes of devices, such as fine pitch light emitting diode (LED) array electrophotographic print heads, which place premiums on precision alignment, high electrical interconnect density, close die placement, and low cost. The manufacturing feasibility of such an array was investigated, with particular emphasis on the quality of surface tension induced self-alignment inherent in solder bump bonding. An array of surface emitting LED diode array chips was fabricated employing 75- mu m-diameter solder bumps on 156- mu m pitch. The chips were spaced 15 mu m edge-to-edge, face down, on a glass substrate patterned with thin-film metallization. Chip-to-substrate alignment errors in the X-Y plane were found to be under 1.5 mu m with a standard deviation of under 1.0 mu m, well below the 10-15- mu m error typical of the standard mechanical alignment method. Improvements in light output uniformity and a reduction in scattered light over arrays manufactured with conventional die placement and wire bonding were also observed.<>
Sponsorship	IEEE Electronic Industries Alliance American Society of Mechanical Engineering (ASME) NBS SAE
Starting Page	977
Ending Page	982
Page Count	6
File Size	593239
File Format	PDF
ISSN	01486411
Volume Number	15
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-12-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optical interconnections Packaging Light emitting diodes Optical scattering Optical arrays Manufacturing Bonding Stimulated emission Costs Surface tension
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Precision flip-chip solder bump interconnects for optical packaging

Design and fabrication of 600 DPI light-emitting diode printheads using precision flip-chip solder bump technology

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

A fluxless flip-chip bonding for VCSEL arrays using silver-coated indium solder bumps

Self-aligned Assembly Technology For Optical Devices Using AuSn Solder Bumps Flip-chip Bonding

Cost analysis: solder bumped flip chip versus wire bonding

High-yield flip-chip bonding and packaging of low-threshold VCSEL arrays on sapphire substrates

Flip Chip Bonding of 68 $times$ 68 MWIR LED Arrays

Low cost solder flip chip

Precision flip-chip solder bump interconnects for optical packaging

Similar Documents

Precision flip-chip solder bump interconnects for optical packaging

Design and fabrication of 600 DPI light-emitting diode printheads using precision flip-chip solder bump technology

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

A fluxless flip-chip bonding for VCSEL arrays using silver-coated indium solder bumps

Self-aligned Assembly Technology For Optical Devices Using AuSn Solder Bumps Flip-chip Bonding

Cost analysis: solder bumped flip chip versus wire bonding

High-yield flip-chip bonding and packaging of low-threshold VCSEL arrays on sapphire substrates

Flip Chip Bonding of 68 $times$ 68 MWIR LED Arrays

Low cost solder flip chip

Precision flip-chip solder bump interconnects for optical packaging