NDLI: Twisted bit-line architectures for multi-megabit DRAMs

Content Provider	IEEE Xplore Digital Library
Author	Hidaka, H. Fujishima, K. Matsuda, Y. Asakura, M. Yoshihara, T.
Copyright Year	1966
Abstract	As the memory cell array of DRAM has been scaled down, inter-bit-line coupling noise has emerged as a serious problem. The signal loss due to this noise is estimated at about 40% of the signal amplitude in a polycide-bit-line 16-Mb DRAM with a technologically attainable scaling scheme. Twisted bit-line architectures to reduce or eliminate the noise are proposed and demonstrated by the soft-error rate improvement of a 1-Mb DRAM. The effective critical charge is improved by 35%, which is attributed not only to the improvement of the signal amplitude but also to the elimination of large coupling noise during the sensing operation. The impact of these twisted bit-line architectures from a scaling viewpoint is also examined, and they are shown to be promising candidates for overcoming the scaling problems of DRAMs.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	21
Ending Page	27
Page Count	7
File Size	791784
File Format	PDF
ISSN	00189200
Volume Number	24
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Capacitance Coupling circuits Noise reduction Circuit noise Noise level Laboratories Large scale integration Research and development Amplitude estimation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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