NDLI: Device Yield in Nb-Nine-Layer Circuit Fabrication Process

Content Provider	IEEE Xplore Digital Library
Author	Hidaka, M. Nagasawa, S. Hinode, K. Satoh, T.
Copyright Year	2002
Abstract	We are investigating device yield in our Nb-nine-layer fabrication process for single-flux-quantum (SFQ) circuits, in which the critical current density of the Nb/AlO_x/ Nb Josephson junction (JJ) is 10 kA/cm² and the minimum JJ size is 1 μm². We fabricated several shift registers (SRs) with different sizes that exhibit bit capacities from 16 to 2560 bits on a chip on many wafers. The SR yields correlate roughly with process defect test results using diagnostic chips, which are included in all wafers and consist of various diagnostic patterns such as for interlayer and intralayer insulations. When the defect number was above a certain level, the SR yield drastically degraded. The other reason of SR yield degradation is poor size uniformity of JJ patterns. The JJ pattern resolutions using our i-line stepper depend on the several-μm-level flatness of wafers. All SRs on a chip consisting of 68 990 JJs operated correctly. We obtained both “good” and “poor” chips without intentional changes of process conditions. The “poor” chip was strongly affected by magnetic flux traps. We believe that determining the cause of this difference is key to fabricating SFQ circuits consisting of 100 000 or more JJs.
Sponsorship	Council on Superconductivity Appl. Superconductivity Conference Inc MIT
Starting Page	1100906
Ending Page	1100906
Page Count	1
File Size	1307679
File Format	PDF
ISSN	10518223
Volume Number	23
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Niobium Superconducting magnets Semiconductor device measurement Magnetic noise Magnetic shielding Integrated circuits Magnetic circuits superconductive integrated circuits Magnetic flux trap process reliability single-flux-quantum
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer

Fabrication Technique of Single Flux Quantum ALU by Using Nb Trilayer

Fabrication process of planarized multi-layer Nb integrated circuits

Improvements in Fabrication Process for Nb-Based Single Flux Quantum Circuits in Japan

Research on Effective Moat Configuration for Nb Multi-Layer Device Structure

Improvement of Fabrication Process for 10-${rm kA/cm}^{2}$ Multi-Layer Nb Integrated Circuits

Development of a rapid-single-flux-quantum shift register for applications in RF noise power metrology

Passive Phase Shifter for Superconducting Josephson Circuits

Process-Induced Variability of ${rm Nb/Al}/{rm AlO}_{rm x}/{rm Nb}$ Junctions in Superconductor Integrated Circuits and Protection Against It

Device Yield in Nb-Nine-Layer Circuit Fabrication Process

Similar Documents

Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer

Fabrication Technique of Single Flux Quantum ALU by Using Nb Trilayer

Fabrication process of planarized multi-layer Nb integrated circuits

Improvements in Fabrication Process for Nb-Based Single Flux Quantum Circuits in Japan

Research on Effective Moat Configuration for Nb Multi-Layer Device Structure

Improvement of Fabrication Process for 10-${rm kA/cm}^{2}$ Multi-Layer Nb Integrated Circuits

Development of a rapid-single-flux-quantum shift register for applications in RF noise power metrology

Passive Phase Shifter for Superconducting Josephson Circuits

Process-Induced Variability of ${rm Nb/Al}/{rm AlO}_{rm x}/{rm Nb}$ Junctions in Superconductor Integrated Circuits and Protection Against It

Device Yield in Nb-Nine-Layer Circuit Fabrication Process