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Wiring viterbi decoders (splitting debruijn graphs)
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Pollara, F. Dolinar, S. Collins, O. Statman, J. |
| Copyright Year | 1989 |
| Description | A new Viterbi decoder, capable of decoding convolutional codes with constraint lengths up to 15, is under development for the Deep Space Network (DSN). A key feature of this decoder is a two-level partitioning of the Viterbi state diagram into identical subgraphs. The larger subgraphs correspond to circuit boards, while the smaller subgraphs correspond to Very Large Scale Integration (VLSI) chips. The full decoder is built from identical boards, which in turn are built from identical chips. The resulting system is modular and hierarchical. The decoder is easy to implement, test, and repair because it uses a single VLSI chip design and a single board design. The partitioning is completely general in the sense that an appropriate number of boards or chips may be wired together to implement a Viterbi decoder of any size greater than or equal to the size of the module. |
| File Size | 666295 |
| Page Count | 11 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19890010088 |
| Archival Resource Key | ark:/13960/t9h46mx61 |
| Language | English |
| Publisher Date | 1989-02-15 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Wiring Deep Space Network Hierarchies Very Large Scale Integration Circuit Boards Chips Electronics Architecture Computers Design Analysis Graphs Charts Decoders Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |
