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A single chip vlsi reed-solomon decoder
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Shao, H. M. Reed, I. S. Deutsch, L. J. Truong, T. K. Hsu, I. S. |
| Copyright Year | 1986 |
| Description | A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a time domain algorithm. A new architecture that implements such an algorithm permits efficient pipeline processing with minimum circuitry. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is implemented by a new architecture that maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and a significant reduction in silicon area, therefore making it possible to build a pipeline (31,15)RS decoder on a single VLSI chip. |
| File Size | 342744 |
| Page Count | 9 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19860013320 |
| Archival Resource Key | ark:/13960/t1kh5g818 |
| Language | English |
| Publisher Date | 1986-02-15 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Errors Algorithms Very Large Scale Integration Polynomials Chips Electronics Pipelining Computers Decoders Circuit Diagrams Integral Transformations Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Article |
