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A comparison of methods for dpll loop filter design
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Hurd, W. J. Aguirre, S. Kumar, R. Statman, J. |
| Copyright Year | 1986 |
| Description | Four design methodologies for loop filters for a class of digital phase-locked loops (DPLLs) are presented. The first design maps an optimum analog filter into the digital domain; the second approach designs a filter that minimizes in discrete time weighted combination of the variance of the phase error due to noise and the sum square of the deterministic phase error component; the third method uses Kalman filter estimation theory to design a filter composed of a least squares fading memory estimator and a predictor. The last design relies on classical theory, including rules for the design of compensators. Linear analysis is used throughout the article to compare different designs, and includes stability, steady state performance and transient behavior of the loops. Design methodology is not critical when the loop update rate can be made high relative to loop bandwidth, as the performance approaches that of continuous time. For low update rates, however, the miminization method is significantly superior to the other methods. |
| File Size | 615998 |
| Page Count | 11 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19870005909 |
| Archival Resource Key | ark:/13960/t6g20w03p |
| Language | English |
| Publisher Date | 1986-11-15 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Deep Space Network Filters Digital Systems Phase Locked Systems Analog Circuits Microelectronics Loops Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Article |
