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Digital phase-locked loop
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Copyright Year | 1975 |
| Description | An digital phase-locked loop is provided for deriving a loop output signal from an accumulator output terminal. A phase detecting exclusive OR gate is fed by the loop digital input and output signals. The output of the phase detector is a bi-level digital signal having a duty cycle indicative of the relative phase of the input and output signals. The accumulator is incremented at a first rate in response to a first output level of the phase detector and at a second rate in response to a second output level of the phase detector. |
| File Size | 586242 |
| Page Count | 9 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19750016968 |
| Archival Resource Key | ark:/13960/t8cg4gv17 |
| Language | English |
| Publisher Date | 1975-05-13 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Analog Circuits Closed Cycles Phase Locked Systems Accumulators Computers Digital Techniques Computer Design Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Patent |
