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Characterization of silicon-gate cmos/sos integrated circuits processed with ion implantation
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Woo, D. S. |
| Copyright Year | 1980 |
| Description | The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced. |
| File Size | 968919 |
| Page Count | 29 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19830003594 |
| Archival Resource Key | ark:/13960/t79s6k60f |
| Language | English |
| Publisher Date | 1980-05-01 |
| Access Restriction | Open |
| Subject Keyword | Solid-state Physics Solar Cells Gates Circuits Integrated Circuits Ion Implantation Semiconductor Junctions Metallizing P-type Semiconductors Silicon Sos Semiconductors Surface Finishing Surface Layers Cmos Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |
