Loading...
Please wait, while we are loading the content...
Similar Documents
Characterization of silicon-gate cmos/sos integrated circuits processed with ion implantation (Document No: 19840021018)
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Woo, D. S. |
| Copyright Year | 1982 |
| Description | The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing. |
| File Size | 4281606 |
| Page Count | 19 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19840021018 |
| Archival Resource Key | ark:/13960/t6n05zv01 |
| Language | English |
| Publisher Date | 1982-01-01 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Gates Circuits Ion Implantation Format Electron Beams Aluminum Coding Wafers Microelectronics Sos Semiconductors Masks Computer Aided Design Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |
