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The validation buffer out-of-order retirement microarchitecture (2007)
| Content Provider | CiteSeerX |
|---|---|
| Author | Petit, S. Sahuquillo, J. López, P. Duato, J. |
| Abstract | Current superscalar processors commit instructions in program order by using a reorder buffer (ROB). The ROB provides support for speculation, precise exceptions, and register reclamation. However, committing instructions in program order may lead to significant performance degradation if a long latency operation blocks the ROB head. Several proposals have been published to deal with this problem. Most of them retire instructions speculatively. However, as speculation may fail, checkpoints are required in order to rollback the processor to a precise state, which requires both extra hardware to manage checkpoints and the enlargement of other major processor structures, which in turn might impact the processor cycle. This paper focuses on out-of-order commit in a nonspeculative way, thus avoiding checkpoints. To this end, we replace the ROB with a validation buffer (VB) structure. This structure keeps dispatched instructions until they are nonspeculative or mispeculated, which allows an early retirement. By doing so, the performance bottleneck is largely alleviated. An aggressive register reclamation mechanism targeted to this microarchitecture is also devised. As experimental results show, the VB structure is much more efficient than a typical ROB since, with only 32 entries, it achieves a performance close to an in-order commit microprocessor using a 256-entry ROB. 1 |
| File Format | |
| Language | English |
| Publisher Date | 2007-01-01 |
| Access Restriction | Open |
| Subject Keyword | Validation Buffer Out-of-order Retirement Microarchitecture Program Order Significant Performance Degradation Performance Bottleneck Validation Buffer Precise Exception Out-of-order Commit Rob Head Experimental Result Vb Structure Dispatched Instruction Current Superscalar Processor Extra Hardware Processor Cycle Reorder Buffer Typical Rob Precise State Early Retirement Major Processor Structure Long Latency Operation 256-entry Rob In-order Commit Microprocessor Nonspeculative Way Aggressive Register Reclamation Mechanism Several Proposal |
| Content Type | Text |
| Resource Type | Technical Report |
