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Oracle Corporation Intel Corporation
| Content Provider | CiteSeerX |
|---|---|
| Author | Bhati, Ishwar |
| Abstract | Capacitive DRAM cells require periodic refreshing to preserve data integrity. In JEDEC DDRx devices, a refresh operation is carried out via an auto-refresh command, which refreshes multiple rows from multiple banks simultaneously. The internal implementation of auto-refresh is completely opaque outside the DRAM—all the memory controller can do is to instruct the DRAM to refresh itself— the DRAM handles all else, in particular determining which rows in which banks are to be refreshed. This is in conflict with a large body of research on reducing the refresh overhead, in which the memory controller needs fine-grained control over which regions of the memory are refreshed. For example, prior works exploit the fact that a subset of DRAM rows can be refreshed at a |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Memory Controller Auto-refresh Command Jedec Ddrx Device Data Integrity Multiple Row Large Body Refresh Operation Capacitive Dram Cell Periodic Refreshing Multiple Bank Dram Row Refresh Overhead Internal Implementation Fine-grained Control |
| Content Type | Text |
